http://austinpublishinggroup.com/austin-internal-medicine/fulltext/aim-v1-id1011.php

The development in the field of bio sensing of biochemical molecules has been rapid during the recent years. Among many sensing technologies, Silicon Nanowire (SiNW)-based Field-Effect Transistors (FETs) have been shown to be as one of the most promising building blocks for the next generation electrical circuits in recognizing a wide range of biological and chemical targets. They have been successfully used in the detection of, for example, DNA, pH, protein, glucose, virus, and vapor. Despite the significant developments in the area, it seems, however, that the underlying detection mechanism and dynamics of the SiNW FETs are not well defined, and further studies are required. Due to the large surfaceto- volume ratio, one-dimensional nanostructures are considered as one of the best candidates for ultra-sensitive sensors. SiNW FETs have been experimentally demonstrated for direct, label-free, high sensitive, highly selective, and real-time detection of biological and chemical targets at very low concentrations. The most typical configuration of this device uses a nanowire as the essential building block bonding two ends of the nanowire to a solid substrate to create a SiNW FET.

Nanowire (NW) has attracted wide attention, and analyses that focus on various aspects of the device operation have accumulated. We have offered an experimental and analytical method to observe the poly silicon NW MOSFET threshold voltage based on a simple ballistic MOSFET modeling. This paper is intended to incorporate scattering effects into the ballistic modeling and to provide a compact model of the quasi-ballistic Si NW MOSFET. Silicon NW MOSFETs attract wide attention as a promising Nano device for future highdensity LSI application. For development of the device including the circuit application, a handy tool that affords accurate prediction of device characteristics is indispensable.

The device samples were manufactured on standard 6-in. p-type wafers. A proposed hybrid sensor/memory/CMOS poly-Si nanowire structure is illustrated in (Figure 1). The bottom-gate poly-Si nanowire formation can be inserted specifically after metallization of the back-end process (BEOL). At the beginning, buried oxide was deposited on a substrate surface as the gate dielectric of nanowire FETs. A 50-nm polysilicon layer was then deposited using the CVD process. Subsequently, the poly-Si wire was patterned by the standard I-line stepper of the CMOS semiconducting process. By using reactive plasma etching for photoresist trimming followed by silicon etching, the NW dimension was scaled to a level of approximately 100nm.